The present invention relates, in general, to high or low-temperature, including burn-in, testing of integrated circuits (ICs) using a testing board having thermal characteristics similar to that of a semiconductor wafer used to fabricate the ICs.
After their manufacture, ICs are subjected to various types of testing to verify their reliability and operability. This testing may include exposure and functional testing of the IC to either, or both, high or low temperatures. One of these types of testing done at a high temperature is known as "burn-in testing" and involves the application of an electrical bias or other signals to the IC during an elevated-temperature baking period. The purpose of such burn-in testing is to accelerate the appearance of any latent defects which might otherwise only show up after many hours of IC use. In the past, burn-in testing often has been performed on ICs that have already been placed into a final package. However, the trend in burn-in testing is to perform such testing at the semiconductor wafer level. This can be done by either testing of IC die prior to their separation from a processed wafer or testing of individual IC die after separation from the wafer, but prior to packaging. One advantage of testing at the wafer level is a reduction in the cost of the testing due to the elimination of interposers or other intermediate contact assemblies that have been required in the past to connect a burn-in testing circuit to the ICs on the wafer. Another advantage of wafer level testing is the ability to more quickly provide feedback to the wafer fabrication line based on the results of functional and burn-in testing at the end of the line.
It is generally desirable that burn-in testing be performed at higher temperatures, for example about 150.degree. C. This is so because such testing can be performed in a shorter time period than at lower temperatures. One of the requirements of a suitable testing board is that it be formed of a material that is stable at these higher temperatures. One such material is a silica or ceramic-filled fluoropolymer such as teflon. This material has a fairly low dielectric constant and is stable at temperatures up to 200.degree. C. However, one problem with such a fluoropolymer material is that it has a coefficient of thermal expansion (CTE) of about 17 ppm/.degree.C., which is significantly greater than the CTE of silicon, which is about 3 ppm/.degree.C. Thus, it is difficult to ensure alignment and good contact between the testing board and the input/output pads on each of the ICs across the full surface of the wafer as the testing board and wafer thermally expand and contract. The use of silicon as a testing board material might avoid the disadvantages of the mismatch in CTEs discussed above, but a silicon testing board is more expensive to build than, and is not available in the large area formats commonly available for, a fluoropolymer board.
Testing boards are also used to perform cold, or low, temperature testing of ICs. As for burn-in testing above, it is desirable to avoid a mismatch in CTEs when performing cold testing. A mismatch in CTEs can result in poor contact with the IC under test.
Another problem faced by prior wafer-level testing boards is the difficulty in achieving good planarity of the surface of the board used to contact the semiconductor wafer. Because it is desirable for a hot/cold temperature testing board to make contact to a large number of integrated circuits on the wafer, it is important to provide a testing board that remains substantially planar during the varying temperatures used during testing. If good planarity is not achieved, then many ICs on the wafer will not be properly tested due to poor electrical connections with the contacts on the testing board.
Accordingly, there is a need for a hot or cold temperature/functional testing board having thermal expansion characteristics substantially similar to that of the semiconductor wafer containing a plurality of ICs to be tested. Also, it is preferable that such a testing board be less expensive to manufacture than a testing board made primarily from silicon. Further, it is desirable that such a testing board have a surface for contacting the ICs that is substantially planar.